module Writeback(
  input enable,
  output ready,
//from memnory stage
  input [31:0] inst_i,
  input [63:0] pc_i,
  input [1:0] other_op_i,
  input difftest_raise_hard_intr_i,
  input difftest_memory_op_i,
  input [63:0] difftest_memory_addr_i,
  input [63:0] dest_data_i,
  input [4:0] dest_i,
  input dest_valid_i,
  
  input [63:0] load_data_i,
  input load_valid_i,

//to decode stage   
  output [31:0] inst_o,
  output [63:0] pc_o,
  output [1:0] other_op_o,
  output difftest_raise_hard_intr_o,
  output difftest_memory_op_o,
  output [63:0] difftest_memory_addr_o,
  output [4:0] waddr,
  output wen,
  output [63:0] wdata
);

  assign wen = dest_valid_i|load_valid_i;
  assign waddr = dest_i;
  assign wdata = {64{dest_valid_i}}&dest_data_i | {64{load_valid_i}}&load_data_i;
  assign ready = enable;

  assign pc_o = pc_i;
  assign inst_o = inst_i;
  assign other_op_o = other_op_i;
  assign difftest_raise_hard_intr_o = difftest_raise_hard_intr_i;
  assign difftest_memory_op_o = difftest_memory_op_i;
  assign difftest_memory_addr_o = difftest_memory_addr_i;
endmodule
